2nm MIPI D-PHY c-phy IP

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Compare 2 IP from 2 vendors (1 - 2)
  • PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
    • The PCIe 5.0/6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 5.0/6.0 specification.
    • This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
    • It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
    Block Diagram -- PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
  • Standard Cell
    • Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported.
    • More than 3500 fully customizable cells are available, and each has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.
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Semiconductor IP