2.5D GPU IP

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Compare 9 IP from 2 vendors (1 - 9)
  • 2.5D GPU IP Core - API Support: Vivante VGLite API, OpenVG 1.1
    • Embedded Linux support
    • Pixel Rate (Pixel/Cycle): 1
    • Display Resolution: up to 4K
    • API Support: Vivante VGLite API, OpenVG 1.1
  • 2.5D GPU IP Core - API Support: Vector Graphics, VGLite API
    • Embedded Linux support
    • Pixel Rate (Pixel/Cycle): 1
    • Display Resolution: up to 4K
    • API Support: Vector Graphics, VGLite API
  • Vector Graphics IP
    • Display Resolution: Up to 4K
    • ROPS (Pixels Per Cycle) : 1
    • API Support:Vector Graphics VGLite API
    • Embedded Linux Support
  • TSMC N3P Source Sync 3DIO PHY
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N5 Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • Synopsys Synthesizable 3DIO IP for Flexible Physical Implementation
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • 3DIO PHY IP for TSMC N5
    • Optimized for heterogeneous integration in 3D stacking
    • TSMC N5
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Semiconductor IP