LPDDR3 PHY IP
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LPDDR3 PHY IP
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LPDDR3 PHY IP
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LPDDR3 IP solution
- Compatible with LPDDR3 up to 2133Mbps
- AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
- DFI compliant interface between controller and PHY
- Support ECC (error correcting code)
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LPDDR3 Synthesizable Transactor
- Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C
- Supports all the LPDDR3 commands as per the specs
- Supports up to 32GB device density
- Supports the following devices:
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LPDDR3 DFI Synthesizable Transactor
- Compliant with DFI version 3.1 or higher Specifications.
- Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
- Supports for Read data-eye training.
- Supports for Read gate training.
