Analog IP for TSMC
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1,951
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1.7GHz Multiplying PLL on TSMC 28nm
- Including Loop-filter
- VCO operating range : 850MHz - 1700 MHz
- Output frequency range : 850MHz -1700 MHz
- Input frequency range : 9.6MHz - 216MHz
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5GHz Multiplying PLL on TSMC 28nm
- Including Loop-filter
- VCO operating range : 2500MHz - 5000 MHz
- Output frequency range : 1250MHz - 2500 MHz
- Input frequency range : 12MHz - 320 MHz
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1.8GHz SSCG PLL on TSMC 28nm HPC+
- Including Loop-filter
- VCO operating range : 900MHz - 1800 MHz
- Output frequency range : 900MHz-1800 MHz
- Input frequency range : 12MHz - 192MHz
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3.2GHz SSCG PLL on TSMC 12nm
- Including Loop filter
- VCO operating range : 1600MHz- 3200MHz
- Output frequency range: 400MHz- 3200MHz
- Input frequency range : 10MHz- 200MHz
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4.3GHz SSCG PLL on TSMC 7nm
- Including Loop filter
- VCO operating range : 2000MHz-4300MHz
- Output frequency range: 500MHz-4300MHz
- Input frequency range : 10MHz- 200MHz
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32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
- This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
- Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
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32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
- PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
- Full rate CMOS differential input data, centered with half-rate CMOS differential clock
- Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.
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106dB, 24-bit audio three-channels ADC in TSMC 40uLP
- tADC106-SW1-LR.01_TSMC_40_uLP is a mixed (analog and digital) Virtual Component (ViC) in TSMC 40uLP containing a three-channel ADC and additional functions offering an ideal mixed signal front end for low power and high quality audio applications.
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Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode
- Ideal regulator for power and voltage islets
- Secured integration in the SoC Embedded RCU (Regulator Control Unit) to manage booting and mode transitions and to ensure data integrity
- Configurable output drive before delivery to fit the application
- Performances in sleep mode: qLR with low quiescent current: 0.2 uA
