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18
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for SMIC
from 5 vendors
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10)
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Linear Battery Charger
- CC/CV charge
- Trickle charge when battery voltage is low
- Adjustable charging current with temperature compensation
- Highly accurate end-of-charge voltage
- Load short protection
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M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
- Pure core voltage design
- Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
- Compatible with commonly used crystal oscillator frequencies
- Good power noise immunity for period jitter (< ±15%/V)
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Power on reset for 1.8V - SMIC 0.18um
- Area: 0.033mm2
- Treset (Minimum reset duration): 60us
- Vth- (Lower threshold): 1.36V
- Vth+ (Higher threshold): 1.49V
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Power-on reset for 3.3V - SMIC 0.18um
- Area: 0.031mm2
- Treset (Minimum reset duration): 60us
- Vth- (Lower threshold): 2.3V
- Vth+ (Higher threshold): 2.5V
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POR - SMIC 55nm Eflash
- Internal counter to set power-on-reset time; 2.5V device only;
- No static current; Internal low voltage detector (1.8V)
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SMIC 0.18¦Ìm 5v-3.3v/1.8v Power Regulator
- Process: SMIC 0.18¦Ìm 3.3v/1.8v 1P5M Logic process (This IP can work in both generic 0.18um process & 0.162um shrink process without any design change.)
- Input voltage: 2.7~5.5V
- Output voltage: 3.3v +/-5%(when VIN>3.6V); VIN-0.3V(when VIN<3.6V) 1.8v+/-5%
- Maximum output current: IV18max=100mA; IV33max =200mA
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Low (Leakage) Power Memory
- 55% lower standby leakage power
- 6% lower active power (at same memory access speed)
- 10% smaller in size
- Supports Retention and Power Down modes, with 35% lower leakage in Retention mode
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Low (Active) Power Memory
- 35% lower active power
- 5% higher performance (at the same power level)
- Supports Retention and Power Down modes, with 65% lower leakage in Power Down mode
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SMIC 0.18um Low Leakage Process
- Process: SMIC 0.18um low leakage 1.8V/3.3V 1P4M logic process
- Input voltage: 3.0v~3.6v
- Output voltage: VIN-0.15~VIN when the supply voltage VIN is between 3.0V~3.6V
- Maximum output current: 100mA
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SMIC 0.18um Low Leakage Power_On Reset
- Process: SMIC0.18 Low Leakage 1P4M logic process
- Operating voltage range: AVDD18: 0~2V AVDD33: 0~3.6V
- Operating temperature range: -40~125 c
- No external components required (VREF and IBN are reference voltage and current each from another on-chip analog block)