Zynq UltraScale+ MPSoC Processing System IP
Overview
Xilinx provides the Processing System IP Wrapper for the Zynq UltraScale+ MPSoC to accelerate your design and its configuration for your embedded products
Key Features
- Enable/Disable I/O Peripherals (IOP)
- Enable/Disable AXI I/O ports (AIO)
- MIO Configuration
- Extended MULTIPLE USE I/Os (EMIO)
- DDR Configuration
- Security and Isolation Configuration
- Interconnect logic for Vivado IP - PS interface
- PL Clocks and Interrupts
Technical Specifications
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