XMBus Verification IP

Overview

XMBus(Extended Management Bus) Verification IP provides an smart way to verify the XMBus bi-directional two-wire bus. The SmartDV's XMBus Verification IP is fully compliant with version 0.5 of the XMBus Specifications and provides the following features.

XMBus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

XMBus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports XMBus specifications version 0.5.
Supports XMBus device types: Master, Slave.
Start, repeated start and stop for all possible transfers.
Supports 7bit configurable Slave address.
Supports 7bit configurable Broadcast Slave address.
Supports write/read XMBus commands as per the specifications.
Supports Bus reset.
Supports Packet Error Checking(PEC).
Supports PEC enable/disable.
Supports Parity error checking.
Supports Parity error checking enable/disable.
Supports Read pointer mode.
Supports In-Band Interrupt mechanism.
Supports command encoding for 1 byte,2 bytes,4 bytes and 16 bytes.
Supports switching between I2C and XMBus mode.
Supports Master/Slave arbitration.
Supports Error handling during PEC Enabled/Disabled.

Write Command Data Packet Error Handling
Read Command Data Packet Error Handling

Supports Error reporting by 2-ways,

Host reading the status register.
By using In band Interrupt.
Host ACK followed by device payload.
Host NACK followed by STOP.

Built-in monitors for protocol checking, including a global bus monitor.
Functional coverage to cover all functionality of XMBus Slave and Master.
Callbacks in Master and Slave for various events.
Status counters for various events in bus.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
XMBus Verification IP comes with complete testsuite to test every feature of XMBus specification.

Benefits

Faster testbench development and more complete verification of XMBus designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the XMBus testcases to certify XMBus Master/Slave device.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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