Xilinx Ultra Scale Plus SATA HOST IP
Overview
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_HOST_GTHE4 IP is compliant with Serial ATA III specification and signaling rate is 6Gbs. The LDS_SATA3_HOST_GTHE4 IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
Key Features
- Physical Layer features
- Detect OOB and COMWAKE
- Detect the K28.5 comma character and provides a 32 bit parallel output
- Power management mode handled by state machine (shared between Phy and Link layer)
- Provides error indication to upper layers
- 8b/10b encoding and decoding in Xilinx GTHE4
- 6Gbs Speed
- Link Layer features
- Scrambling of tx data and descrambling of rx data
- CRC 32 calculation and check
- Report transmission status and error to Transport Layer
- Enable BIST loopback and pattern generation modes
- Auto inserted hold primitive to avoid FIFO overflow and underflow
- Partial and slumber power management modes
- CONT primitive management in receive and transmit
- The interface between the link layer and the transport layer is 32-bit wide
- Transport Layer features
- 48-bits sector address
- Programmed IO (PIO) and DMA modes
- Support BIST FIS transmission and reception
- Automatic error FIS retry capability
- Implement Shadow Registers and SATA SuperSet registers
- Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
- DMA interface can be connected easily to memory space or FIFOs (FIFO interface provided)
- Support DMA Abort primitive
- NCQ Support.
Block Diagram
Applications
- Embedded Recorder
Deliverables
- Source Code
- Encrypted Code
Technical Specifications
Maturity
Good
Availability
Now