Xilinx Kintex 7 NVME HOST IP

Overview

Key Features

• - PCIe RP and EP register configuration is done automatically.
• - NVMe register configuration is done automatically.
• - Able to manage 8 Name Spaces.
• - Able to manage until 16 IO Queue to fit specific user requirement.
• o Each IO Queue is independent.
• - Able to manage 512Bytes or 4096Bytes sector size.
• - Able to run nearly all Admin command in parallel of IO Queue.
• - Many IO command already pre-defined to ease use of the IP.
• - Configurable IO Queue buffer size to fit user memory requirement in case of small density FPGA: 32KB, 64KB, 128KB or 256KB.
• - Able to read all PCIe RP and EP registers.
• - Easy connection to embedded Root Port PCIe IP through AXI bus.

Block Diagram

Applications

• Embedded recording.

Deliverables

• Source code.
• Encrypted source code.

Technical Specifications