The wide range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. The PLLs are designed for digital logic processes and uses robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core devices only, removing constraints on the choice of IO devices within the standard logic process. The PLL is the smallest PLL in the industry and resides inside the IO ring of two analog power supply pads, occupying no core area. In order to minimize noise coupling, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any industry standard IO pad pitch and is available for both staggered and in-line IO’s.
PLL Operational Range Description Symbol Min Typ Max Units Input frequency FREF 5 200 MHz Post-Divide Reference Frequency FPFD 5 200 MHz VCO Frequency FVCO 1000 MHz Output Frequency FOUT 20 1000 MHz Output Duty Cycle (FOUT <=500MHz) tDO 45 55 % Output Duty Cycle (FOUT >500MHz) tDO 40 60 % Lock Time tLOCK 100 us Total area of macro (excluding bond pad area) A 0.027 sq.mm Depends on size of IO slots Chip core area requirement CA 0 sq.mm Total Power IDD 1 mA Operational Voltage (Digital) VOP 1.08 1.2 1.32 V Operational Temperature TOP 25 125 C Functional Temperature TFUN -40 125 C Table 1: PLL Operational Range