WIDE IO Synthesizable Transactor provides a smart way to verify the WIDE IO component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's WIDE IO Synthesizable Transactor is fully compliant with standard JESD229 Specification and provides the following features.
WIDE IO Synthesizable Transactor
Overview
Key Features
- Supports 100% of WIDE IO protocol standard JESD229
- Supports all the WIDE IO commands as per the specs
- Quickly validates the implementation of the WIDE IO standard JESD229
- Supports programmable burst lengths: 2, 4
- Checks for following:
- Check-points include power up, initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports all mode registers programming
- Supports write data mask
- Supports power down features
- Supports full-timing as well as behavioral versions in one model
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the WIDE IO testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes