The WDT Verification IP provides a simple verification solution to verify the components interfacing with the WDT the VIP supports Verilog and System Verilog with Universal Verification Methodology (UVM). WDT compatible UVM based, a BUS monitor. BUS monitor monitors all the transfers that are going on the WDT bus.
WDT Verification IP
Overview
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of Conformance and Regression Test Suites.
- 24X5 customer support.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment.
Block Diagram
