VME System Controller

Overview

Key Features

• System Controller
• Bus Arbiter
• Fixed priority
• Round robin
• Bus Timer
• Programmable 1-255 μs timeout
• SYSCLOCK* driver
• SYSFAIL* driver
• First Slot Detector
• IACK daisy-chain driver
• Master Interface
• Coupled transfers for single data cycles
• Addressing modes: A16, A24, A32
• Data types: D08(EO), D16, D32
• Access modes: Read, write, read-modify-write
• DMA Engine
• Used to transfer data blocks
• Addressing modes: A16, A24, A32
• Data modes: D08(EO), D16, D32, D32-BLT, D64-MBLT
• Supports data read-ahead and posted write to increase throughout
• Selectable constant local bus address for DMA transfers to/from FIFOs
• Address translation
• Slave Interface
• Addressing modes: A16, A24, A32
• Data types: D08(EO), D16, D32, D32-BLT, D64-MBLT
• Access modes: Read, write, read-modify-write
• Selectable rescinding DTACK
• Provides big-endian to little-endian conversion option
• Interrupt Handler
• Automatically fetches STATUS/ID vector from pending VME interrupt requests
• Supports D08(O), D16, and D32
• Interrupter
• D08(O)
• Software interrupt request (ROAK)
• User interrupt request (RORA)
• Programmable interrupt level
• Bus Requester
• RWD (release when done) and ROR (release on request) arbitration schemes
• FAIR requester
• Supports early withdrawal of bus request
• Local Bus Interface
• Fully synchronous bus interface for user logic
• User selectable wait-states
• Optional big-endian to little-endian conversion
• CR/CSR
• Contains address decoding for CR/CSR space
• Local CSR configuration registers

Benefits

• The VMESCmodule is a VME System Controller core designed for FPGA and ASIC integrations.
• The core contains VME Slave and Master functions as well as System Controller features such as bus timer, arbiter, IACK daisy-chain driver, system clock driver, and provisioning for CR/CSR.
• The core contains all functionality needed for a VME system controller design. It can as well be used in situations where only VME Master or VME Slave functions are needed.
• The core can be used together with application specific logic to mitigate technology obsolescence. The Module is an excellent starting point for future VME designs.

Block Diagram

Deliverables

• VHDL RTL code
• Self-verifying system-level testbench
• Simulation and synthesis scripts
• Synthesis information
• User guide
• Hotline Support by means of phone, fax and e-mail

Technical Specifications