Video Output Port IP Core is a compact and high-performance functional block for embedded system that collects and outputs graphical video data to video display controller.
Video Output Port (VOP) IP Core provides a multi-layer video data output from memory to the display device. The main functions of IP Core are - direct memory access, data buffering, mixing images with alpha channel overlay, generation of clock signals to the display device.
IP core is designed to build systems that require hardware acceleration for graphics output.
Video Output Port IP Core
Overview
Key Features
- Pixel format: ARGB 32bpp;
- Number of layers – parameter of synthesis;
- Layer mixing: ◦with the addition of an alpha channel;
- with previously added an alpha channel;
- with the addition of a constant alpha channel.
- Changing the size and position of the video window for each layer;
- Pan and zoom (image size is larger than the window);
- Hardware cursor.
Deliverables
- IP Core is available as either netlist or VHDL source codes. It includes all that requires for easy implementation in the customer projects. The delivery includes:
- Synthesized netlist for target FPGA device;
- Testbench;
- Place@Rout script;
- Simulation script
- Detailed specification and implementation guide.
Technical Specifications
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