The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displays over HDMI 2.1, MIPI DSI, and VESA DisplayPort links. The IP enables designers to incorporate visually lossless data compression between the SoC and display to maximize video bandwidth and optimize power, and area for mobile, automotive, and AR/VR applications. The VESA DSC IP, consisting of encoder and decoder, is compliant with the latest VESA DSC 1.2a and 1.1 specifications.
The MIPI DSI Host Controller IP with VESA DSC encoder together with the MIPI D-PHY and C-PHY/D-PHY IP provide a complete, interoperable display solution, enabling designers to lower their risk and cost of integrating the IP into application processors, display bridge integrated circuits (ICs) and multimedia coprocessors.
