This is a configurable reciprocal DSP core for signal processing application on programmable logic devices.
The core operates on streamed data which is reciprocated (inverse value calculated) via a non-traditional, intelligent, innovative design. After an initial output delay equal to the bit width of the input plus 4 clock cycles, the output is also streamed out at a rate of one result per clock cycle.
This DSP engine is written in VHDL, capable of being used on any FPGA/ASIC architecture.
Very Small Form-Factor Division Core
Overview
Key Features
- Optimized design allows customers to target cost efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
Deliverables
- Netlist or synthesizable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- Integration documentation and user guide