USB 3.2 Retimer softcore is designed for use in USB Port/Cable Retimer applications with USB SuperSpeed Plus/SuperSpeed link operations. The IP has been verified in simulation and is synthesis clean for FPGA implementations
USB 3.2 ReTimer
Overview
Key Features
- SuperSpeed Plus @10Gbps with fallback to SuperSpeed @5Gbps
- USB-Link parallel data-path 20bit for SS, and 32bit for SSP
- Implements Digital-PHY PCS as part of the core supporting 8b/10b and 128b/132b codec with scrambler and descrambler, error detection-correction, Clock offset compensation with elasticity buffer, LFPS, full LPM, and compliance-mode
- Easy customization for interface to PMA/SERDES logic and sideband signalling
Block Diagram
Technical Specifications
Maturity
Available on Request
Availability
Available on Request