USB3.2 Gen2x2 xHCI Host Controller

Overview

MosChip USB3.x Host softcore is designed for embedded host applications with USB SSP operations and fall back support of SS and USB2 speed modes over Type-C or native USB host connector. The IP is validated for inter-operability against standard USB devices and has passed all USB3CV functional tests. The parametrized design allows IP configuration for target application needs

Key Features

Spec reference:
Intel xHCI revision 1.1
USB3.2 revision 1.0 for x2 lane SSP/SS, USB2 HS/FS /LS speed modes
USB UTMI+ and ULPI
AMBA AXI4
Intel PIPE v4.3
SSP x2 lane @20Gbps, SSP x1 lane @10Gbps, SS @5Gbps with fallback to USB2 High/Full /Low Speed modes
USB-Link interface support: PIPE 16/32-bit and UTMI+/ULPI 16/8-bit
Supports BulkStream for UASP applications
Optimized design provides efficient resource utilization, >95% link bandwidth utilization, and lowest power with full power management

Benefits

System interface support: AMBA-AXI4 32/64-bit
Clock domain crossing mechanism between USB and system-bus provides flexibility for easy integration
Optional inbuilt PCS logic with Xilinx Gigabit transceivers provides full USB3-link solution avoiding need for external PHY. Alternatively supports external USB PHY with standard PIPE interface
Optional support for PCIe based system host with external PCIe endpoint core

Block Diagram

Technical Specifications

Maturity

Available on Request

Availability