USB3.2 Device Controller

Overview

MosChip USB 3.2 Device Controller softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Device implementations along with backward compatibility to High/Full speed modes with Type-C or standard USB-Device connector.

Key Features

  • USB Device Controller with protocol-layer and link-layers implementation
  • USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full Speed modes
  • Support PIPE and UTMI+/ULPI interfaces with full link power management
  • AMBA-AXI system-bus interface for configuration-space access and data-path interface with Inbuilt DMA engines that provide enhanced data transfer capability
  • Up to 16 IN and OUT Endpoints including control Endpoint
  • Parameterized design allows configuration of internal buffers based on application needs
  • Clock domain crossing mechanism between USB and XDC/system-bus logic provides flexibility for easy integration

Block Diagram

USB3.2 Device Controller Block Diagram

Deliverables

  • Synthesizable Verilog source code
  • Product reference manual
  • Synthesis constraints reference file
  • Reference design and basic test-bench

Technical Specifications

Maturity
Available on Request
Availability
Available on Request
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Semiconductor IP