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USB TYPE C IIP

Overview

USB Type C interface provides full support for the USB Type C synchronous serial interface, compatible with USB 3.0/2.0 and 1.0 specifications. Through its USB Type C compatibility, it provides a simple interface to a wide range of low-cost devices. USB Type C IIP is proven in FPGA environment. The host interface of the USB Type C can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

USB TYPE C IIP is supported natively in Verilog and VHDL

Key Features

  • Compliant with USB Type-C Cable and Connector Specification 3.0/2.0 and 1.0
  • Supports Debug accessory operation
  • Supports Audio accessory operation
  • Supports Plug Orientation/Cable Twist Detection
  • Supports all the connection fsm states
  • Supports Timers as per specification
  • Supports Counters as per specification
  • Power Delivery support for up to 100W of power through external Power Management IC.
  • Supports up to 10Gbps of data transfer when integrated with USB 3.1 IP
  • Support for 8K video through DisplayPort 1.3/1.4 Alt-Mode
  • Supports USB 2.0
  • Supports USB Type-C Male Connector
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

USB TYPE C IIP Block Diagram

Deliverables

  • The USB Type C interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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