PDM Synthesizable Transactor provides a smart way to verify the PDM bus component of a SOC or a ASIC in Emulator or FPGA platform.
PDM Synthesizable Transactor
Overview
Key Features
- Full PDM Transmitter and Receiver functionality
- Supports 8,10,12,16,20,24,32 bit data precision
- Supports PDM modulator and PDM demodulator
- Supports PDM Digital output
- Supports PDM Error output
- PDM Verification IP comes with complete test suite to test every feature of PDM specification
- Supports fully synthesizable
- Supports static synchronous design
- Supports positive edge clocking and no internal tri-states
- Supports simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the PDM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes