USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)

Overview

A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data connection while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A dedicated PCS can be provided together with the USB 3.1 Type C PHY IP to complete functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. Depending on the customer's choice, PCS is offered as either a hard or soft macro; additionally, the PCS specification will be made available separately. Using a test bench constructed in Verilog HDL, the NC-Verilog simulation software verifies PHY functionality.

Key Features

Support half rate mode (5Gbps) and full rate mode (10Gbps)
Tolerate max +/-7000ppm input frequency offset
32bit/40bit selectable parallel data bus
Programmable transmit amplitude
3 taps/2 taps selectable FFE
Receiver CTLE and One-tap perspective DFE
Build in self-test with PRBS7/31 pattern generation and checker for production test
Integrated on-die termination resistors
Support receiver detection
Support LFPS signal generation and detection
Support Spread Spectrum clock generation and receiving
Flexible reference clock frequency
Do not need any external component
ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
Metal Layer:M1~M7+RDL
Core Voltage: 1.1V
IO Voltage: 3.3V
Silicon Proven in UMC 55SP/EF.

Block Diagram

Deliverables

GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behavior model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports

Technical Specifications

Foundry, Node

UMC 55SP / EF

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