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USB 4.0 Verification IP

Overview

USB 4.0 Verification IP provides a smart way to verify the USB 4.0 component of a SOC or a ASIC. The SmartDV's USB 4.0 Verification IP is fully compliant with standard USB Specification 4.0. The USB 4.0 VIP can be readily customized and optimized for a wide range of specific system applications.

USB 4.0 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

USB 4.0 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with USB4.0 Specification
  • Supports USB4.0 Gen2 and Gen3 Operation
  • Supports constrained randomization of protocol attributes
  • Supports all types of error injection and detection
  • Supports error injection in all the layers of USB 4.0
  • Supports Dual lane
  • Supports Lane margining and Lane de-skew buffer
  • Supports Side band channels
  • Supports SERIAL, PIPE and SERDES Interface
  • Configurable PIPE Interface width 8, 16 or 32 bits
  • Configurable SERDES Interface width 32, 40, 64 and 80 bits
  • Supports Enumeration process to enumerate hub/device
  • Supports 64/66B Encoding and Decoding for Gen2
  • Supports 128/132B Encoding and Decoding for Gen3
  • Supports Scrambler and Descrambler
  • Supports RS-Forward Error Correction (FEC)
  • Supports Clock compensation
  • Supports Spread spectrum clocking
  • Supports jitter
  • Supports Side band register space
  • Supports Configuration register space
  • Supports Lane adapter, Protocol adapter and Control adapter operations
  • Supports Lane initialization process
  • Supports Low power state
  • Supports Lane bonding mechanism
  • Supports Error detection and Recovery mechanism
  • Supports USB4 Link Equalization TxFFE handshake.
  • Supports all the Side Band Channel transactions
  • Supports Sleep and Wake mechanism with respect to the tunneled protocols
  • Supports Hot plug detection and Disconnect detection
  • Supports SKIP Insertion and Removal
  • Supports Time Sync Notification Ordered Set (TSNOS)
  • Supports following Protocol tunneling,
    • USB3 tunneling
    • Display port tunneling
    • PCIE tunneling
  • Supports all the Transport layer packets
  • Supports HEC, ECC and CRC
  • Supports Path Setup & Path Tear-Down mechanism
  • Supports Flow control mechanism
  • Supports all the Control packets
  • Supports all the Notification events
  • Supports Time Synchronization
  • Supports Register Locking mechanism
  • Supports Inter-Domain communication between host interface adapters
  • Supports Thunderbolt related backward compatible operation
  • Supports Qos scheduler
  • Supports Re-timer connectivity models
  • Supports Host interface adapter layer functionality
  • Supports Connection manager behaviour

Benefits

  • Rich set of configuration parameters to control the functionality
  • Faster testbench development and more complete verification of USB 4.0 designs.
  • Easy to use command interface simplifies testbench control and configuration of host and device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

USB 4.0 Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the USB 4.0 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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