USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
Overview
The USB 3.2 Gen2X1 transceiver IP supports all USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps. It conforms with the standards of UTMI+ and PIPE4.0. The USB 3.2 Gen2X1 IP contains high-speed mixed signal circuits to handle Gen2 and Gen1 traffic and is backward compatible with high-speed data rates of 480Mbps, full-speed data rates of 12Mbps, and low-speed data rates of 1.5Mbps. The USB 3.2 Gen2X1 IP provides an active switch to enable bi-directional plug-in and particular functionality (such VBUS setup and USB attachment cable orientation identification) through the CC1/CC2 pins specified in the Type-C connection in order to support the USB Type-C connector.
Key Features
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
- Integrates an active switch to support the orientation-less connection with USB Type-C connector
- Provides an auxiliary CC module IP to support USB Type-C related functions
- Supports both wire-bond and flip-chip package type
- Silicon Proven in UMC 28HPC
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Foundry, Node
UMC 28HPC+
Maturity
In Production
Availability
Immediate
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