USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)

Overview

Key Features

• USB 3.2 Gen2
• 1. Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
• 2. Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
• 3. Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
• 4. Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
• Integrates an active switch to support the orientation-less connection with 5. USB Type-C connectors
• 6. Provides an auxiliary CC module IP to support USB Type-C related functions
• 7. Supports both Wire-bond and flip-chip package types
• 8. Supports internal loop back and BIST functions for mass production testing
• USB 3.2 Gen1
• 1. Worldwide smallest USB 3.2 Gen1x1 PHY IP (e.g. IP size @28HPC+ is smaller than 0.5mm²)
• 2. Fully compliant with Universal Serial Bus USB 3.2 Gen1x1 and 2.0 electrical specifications
• 3. Compliant with PIPE4.0 and UTMI+ specification (Super-Speed, High-Speed, Full-Speed and Low-Speed functions)
• 4. Supports clock inputs from 25MHz crystal oscillator or external 25MHz clock source
• 5. Provides plenty of register controls for TX, RX, SSCG-PLL and CDR electrical parameters
• 6. Silicon proven and mass production IP records

Technical Specifications