USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
Overview
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
Technical Specifications
Foundry, Node
UMC 40nm
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
- USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- USB 3.0 PHY in UMC (65nm, 40nm)
- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)