USB 3.0 xHCI Host Controller

Mature solutions featuring xHCI Host, Device, and Dual-Role

Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 and xHCI Specification, Revision 1.0, the Cadence® Design IP for USB 3.0 xHCI Host Controller operates in SuperSpeed (5Gbps), High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5 Mbps) modes. The PHY interface complies with USB PHY Interface for PCI Express® (PIPE) for USB 3.0, as well as the USB 2.0 Transceiver Macrocell Interface (UTMI+) specification. Combined with the Cadence PHY IP for USB Type-C designs, the Controller IP provides a complete solution for the next generation of USB applications that will make use of the new, flexible USB Type-C connector. The Controller IP is architected to quickly and easily integrate into any SoC as an integrated solution with any Cadence or third-party PHY IP for USB. Host applications access the controller through the industry- standard ARM® AMBA® AXI system bus. The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.