USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
Overview
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
Technical Specifications
Foundry, Node
UMC 28nm
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- USB 3.0 Device IP Core
- CSMC 0.13um USB 1.1 PHY
- USB 3.0 xHCI Host Controller
- Dual-Role Device Controller for USB 3.0
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.