USB 2.0 OTG PHY IP, UMC 55nm LP process
Overview
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process.
Technical Specifications
Short description
USB 2.0 OTG PHY IP, UMC 55nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 55nm LP
UMC
Pre-Silicon:
55nm
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