USB 2.0 OTG PHY IP, UMC 40nm LP process

Overview

OTG USB2.0 UMC 40 nm LP/RVT process.

Technical Specifications

Short description
USB 2.0 OTG PHY IP, UMC 40nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon: 40nm LP
×
Semiconductor IP