USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core

Overview

Our company offers a highly configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications. This controller adheres to the latest industry standards (USB 2.0 and USB OTG) and works seamlessly with existing Windows, Linux, and Android drivers in host mode, minimizing software development effort and risks. It boasts multiple interface options for various systems and offers the flexibility to connect single devices directly or manage multiple devices via hubs. Additionally, optional features like a high-performance DMA engine and a dedicated processor block can be included to optimize performance and reduce development time in device mode. Overall, this versatile controller empowers developers with a wide range of functionalities and customization options, catering to both basic and advanced needs.

Key Features

Support SW controlled host/device role switching.
Support Fullspeed and Lowspeed
Support Control, Bulk, Interrupt and Isochronous Transfer Types
Support L1/L2 power saving modes for USB 2.0 port
Support Hardware LMP Capability and BESL LMP Capability for USB 2.0 ports in host mode
Support MSI/MSI-X Interrupts and Legacy Interrupt
Fully Support for Isochronous Transfer error handling, support error conditions like Isochronous Buffer Overrun, Bandwidth Overrun, Missed Service Error, Ring Overrun/Underrun, Parameter Error, etc. in host mode
Fully Support for Event Data TRB, multiple Event TRBs can be used in one TD in host mode
Fully Support for Hardware Bandwidth Management, support error conditions like Resource Error, Bandwidth Error and Secondary
Bandwidth Error in host mode
xHCI-like ring management, TRB definitions and doorbell mechanism in device mode
Low-MIPS Operational Model.
Pipelined transfer mechanism to achieve continuous data streaming
Innovative Active TRB Prefetching technology to eliminate TRB access latency and improve system performance
Dynamically reconfigurable Endpoint type, software can reconfigure the same Physical Endpoint to operate as Bulk, Interrupt or Isochronous EP
Dynamic data buffer allocation for all endpoints,Tx/Rx Data Buffers can be shared by endpoints to optimize RAM usage
Configurable number of supported device slots (up to 64) in host mode
Configurable number of supported active Endpoints (up to 128) in host mode and Device mode
Configurable numbers of USB 2.0 ports in host mode
Configurable system bus type (AXI4/AXI3/AHB/APB) and width Configurable 2.0 PHY type (PIPE/UTMI+/ULPI) and width.

Block Diagram

Deliverables

The USB 2.0 OTG Controller interface is available in Source and netlist products.
The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

Foundry, Node

Independent, suitable to all 3rd party PHY's

Maturity

In Production

Availability

Immediate

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