USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
Overview
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications. The USB 1.1 PHY IP integrates a semi-digital PLL, which supports clock inputs as low as 32.768KHz. The USB 1.1 PHY IP not only supports standard USB 1.1 features, but also provides multiple clock outputs from 48MHz to 240MHz. It’s ideal for IOT or wearable devices that require basic USB functionalities.
Key Features
- Smallest USB1.1 PHY IP worldwide with PLL inside (<0.1mm²)
- Fully compliant with Universal Serial Bus (USB) 1.1 electrical specification
- Integrated PLL to provide a variety of stand-alone clock outputs
Technical Specifications
Foundry, Node
40nm, 55nm, 90nm ULP process
SMIC
Silicon Proven:
28nm
HKC+
,
55nm
LL
TSMC
Silicon Proven:
40nm
LP
,
55nm
GP
,
55nm
LP
,
55nm
ULP
,
55nm
ULPEF