The Synopsys USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum. The Synopsys USB 1.1 IP offering consists of the USB 1.1 Device and USB 1.1 OHCI Host controllers for integration into SoCs, and Verilog testbench for integration testing. These elements enable quick development of SoC designs incorporating the USB 1.1. The Synopsys USB 1.1 IP is targeted for SoCs requiring the smallest area and lowest power, such as those used in IoT applications.
The DMA in the Device controller and list processor in the Host controller reduce interrupts to the CPU/MPU and bus, reducing power consumption and leaving MIPS and bus bandwidth for other functions.
The Synopsys USB Digital Controllers offer easy integration, reliable data transfer speeds, and low overall power consumption. As the leading supplier of USB IP for more than a decade, Synopsys provides designers with efficient USB IP for cost effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB IP enables us to build a low risk, high quality USB IP solution.
USB 1.1 Digital Controller IP
Overview
Key Features
- Fully supports USB Full Speed and Low Speed (USB 1.1 Speeds)
- Configurable root hub supports 1 to 15 downstream ports
- Integrated DPLL simplifies transceiver integration
- Low gate counts, starting at 30k gates
- Verilog testbench includes a USB test environment, Synopsys Verification IP, and integration tests that can be ported to the system level
- Compatible with the OHCI 1.0 specification, enabling designers to use drivers broadly available from open sources and supported in popular operating systems
Benefits
- Low gate count to save area
- Low-power architecture
- Silicon proven, shipped in billions of units
- Supports USB 1.1 Full and Low Speeds
- Host and Device functions available
- AHB interface for rapid integration
- Save software engineering effort by using drivers for OHCI-compatible Host
Applications
- IoT
- MCUs
- Wearables
- Machine-to-machine
- Automotive
- Touch screen
- Mouse/keyboard
Deliverables
- Synopsys coreConsultant tool
- Verilog RTL source code
- ASIC and FPGA synthesis example scripts
- Verilog testbench
- Databooks
Technical Specifications
Maturity
Available on request
Availability
Available
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