USART Verification IP

Overview

USART Verification IP provides an smart way to verify the USART component of a SOC or a ASIC. The SmartDV's USART Verification IP is fully compliant with standard USART ds8251 Specification and provides the following features.

USART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

USART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Fully compatible with ds8251.
Transmit and receive commands allow the user to transmit and receive USART data.
Configurable Baud rate.
Programmable word length, stop bits, and parity
Offers divide-by-1, -16, or -64 mode
Supports synchronous and asynchronous operation
Uses approximately 528 FLEX logic elements (LEs)
Includes:
- Error detection
- False start bit detection
- Automatic break detection
- Internal and external sync character detection
Full duplex operation.
Fully configurable serial interface.
Data width from 5 bit to 8 bits.
Number of Stop bit configuration.
Parity type,
- Even
- Odd
- No parity
Error Injection and detection for following,
Framing Error
Parity Error
FIFO depth is programmable
Monitor detects following,
- Parity Errors
- Framing Errors
Supports constraints Randomization
Callback in BFM and Monitor for wide range of events to help execute user code.
On-the-fly protocol and data checking
Ability to transmit strings to help verification of SOC.
Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
USART Verification IP comes with complete testsuite to verify each and every feature of USART specification.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Status counters for various events in bus.
Built in functional coverage analysis.

Benefits

Faster testbench development and more complete verification of USART designs.
Easy to use command interface simplifies testbench control and configuration of TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the USART testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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