Unmanaged Ethernet Switch IP Core

Overview

Silicon-Agnostic, Compact and Highly flexible Ethernet Switch IPs

Unmanaged Ethernet Switch IP cores are a family of Ethernet switching IPs from Comcores that provide a variety of configurations, including 1G, 1G/ 10G, 10G, and 10G/25G options. The unmanaged Ethernet switch IP cores family is a size-optimized implementation of non-blocking crossbar switches designed to support wire-speed packet processing and forwarding.

The unmanaged Ethernet switch IP cores family features FCS validation/recalculation, MAC learning/forwarding/ageing and VLAN tagging including implementing a store-and-forward switching architecture.

The number of ports is configurable at compile time, making the unmanaged Ethernet switch IP cores solution highly flexible and the solutions from Comcores are silicon-agnostic, making them suitable for implementation in any ASIC, FPGA, or ASSP technology.

Key Features

Feature Rich
- Automatic MAC address learning and aging
- Support programmable static forwarding entries
- Ethernet Multicast support
- Full duplex Ethernet interfaces
- Supports Access port VLAN and Trunk port VLAN operation
Highly Configurable
- Configurable for up to 16 + 4 ports at compile time
- Supports configurable queuing behaviour, including round-robin and fair queuing
Easy to use
- Compatible with GMII, RGMII, XGMII, and XXVMII interfaces for seamless connection to external Physical Layer devices (PHYs)
- Easy integration with standard Xilinx AXI4 Lite control interface
- Can be implemented with or without an external microcontroller
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs

Block Diagram

Deliverables

Code – VHDL93 – Source code or Encrypted RTL
Documentation – User guide, Programming register description, API description, and Release notes
Basic simulation environment
Timing constraints – XDC format, Synopsys SDC format on request

Technical Specifications

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