The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC). Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
There are options to include support for RS-FEC forward error correction (RSFEC), as per IEEE 802.3 Clause 108, and access to control and status registers through an APB interface.
The PCS IP is engineered to be quickly and easily integrated into any SoC, and to connect seamlessly to a demultiplexed MAC through multiple XGMII (32-bit data, 4-bit control, single clock-edge interfaces). Connection to the SerDes is through a configurable 16, 20, 32, 40, or 64-bit interface.
