Single Channel UART with Scalable Rx-FIFO

Overview

Universal asynchronous receiver and transmitter (UART) using the RS232 protocol are often used to connect peripheral devices to a central controller.
The UARTmodule has one receive and one transmit channel, receive and transmit buffers, an interrupt controller as well as a local bus interface. The built-in receive buffer is configurable in depth, therefore, enabling a gate count and application optimized implementation. The baudrate generator uses a innovative digital controlled oscillator (DCO) to generate baudrates over a wide frequency range. With a system clock of 8MHz, all baudrates from 1200 baud to 115.2 kbaud have an accuracy of better than 0.1%!
To improve glitch rejection, the receiver uses a 3-point input sampling. Format and parity errors are detected and reported.

Key Features

Single channel UART
Flexible baudrate generator
Status and error registers
Scalable RxFIFO (2/4/8/16 bytes deep)
Double buffered TxFIFO
7-bit or 8-bit format
1 or 2 stop bits
Parity enable, even or odd
Local interrupt controller
Supports synchronous bus interfaces such as AMBA APB version 2.0
Full synchronous design
Synthesis Options:

CPU readback enable
CPU bus width
RxFIFO depth

Benefits

For gate-count optimization, the core can be configured to disable the configuration register read-back path. Synthesis options are included to use the core in 8, 16 or 32-bit systems. With a separate APB wrapper, the core can be used in ARM subsystems

Block Diagram

Deliverables

VHDL or Verilog RTL Source Code
Functional Testbench
Synthesys Script
Data Sheet
User Guide
Hotline Support by means of phone, fax and e-mail

Technical Specifications

Foundry, Node

Technology independent

Maturity

Silicon proven in ASIC and FPGA Technologies

Availability

now

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