UniPro 2.0 & Silicon Proven v1.8, v1.61
Key Features
- Compliant with MIPI UniPro Standard v2.0, v1.8 & v1.61 and MPHY standard 3.x, 4.x
- Programmable 1, 2, or 4 data lanes
- Supports M-PHY HS data rates HS-Gear-1,Gear-2, Gear-3, both A/B modes and PWM data rates PWM-G1 to PWM-G7
- Supports End to End flow control.
- Supports all traffic classes.
- Supports preemption of high priority frames.
- Supports maximum of 32 C-Ports.
- Employs Round Robin arbitration across C-Ports.
- Supports group acknowledgement of maximum 16 frames per traffic class.
- Supports retransmission of frames.
- Configurable buffer spaces.
- Supports CSD, CSV.
- Supports UniPro Test Feature.
- TMPI Support.
- Efficient Power Management
Block Diagram
Technical Specifications
Maturity
Silicon Proven, FPGA. Validated, Interop Tested, Design Verified
Availability
Immediate
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