UMC L65LL 65nm Multi Phase DLL - 60MHz-300MHz

Overview

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock. It delivers optimal jitter performance over a wide frequency range. The analog delay-line architecture used in our DLL design is internally isolated from supply noise for very low output jitter. The analog delay line also provides duty cyle correction.

Key Features

  • Designed for high-speed interface applications.
  • Generates precise multi-phase clocks directly from the reference clock.
  • Delivers optimal jitter performance over a wide frequency range.

Deliverables

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Technical Specifications

Foundry, Node
UMC L65LL
UMC
Pre-Silicon: 65nm LL
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Semiconductor IP