UMC L110AELL 110nm Spread Spectrum PLL - 120MHz-600MHz
Overview
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications that require low EMI. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-256 or larger integer divider and a 1-256 or larger fractional divider in the internal feedback path, with as many as 4 bits of precise fractional-N control, and a 1-8 divider at the output. It can generate precise and adjustable frequency spreading depths (1.5% typical and up to around 10%) and rates (30KHz typical). The outputs are 50% duty cycle for all output divider values.
Key Features
- Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.
- Spreading rate and spreading depth are precisely adjustable to allow the designer to dial-in the desired characteristics.
- 15-bit fractional-N feedback divider with 4 bits of precise control.
- Available with multi-phase outputs.
Deliverables
- GDSII (100% DRC and LVS clean)- LVS Spice netlist- Verilog model- Synopsys synthesis model- LEF for clock generator PLL- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
Technical Specifications
Foundry, Node
UMC L110AELL
UMC
Pre-Silicon:
110nm
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