UMC 90nm SP RVT process SSTL18 IO cell library
Overview
UMC 90nm SP RVT process SSTL18 IO cell library
Technical Specifications
Foundry, Node
UMC 90nm
UMC
Pre-Silicon:
90nm
G
,
90nm
LL
,
90nm
SP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- ONFI IO v4.1, 1.2T/s, UMC 22ULL, 1.8V, N/S orientation, H&V cell
- ONFI IO v4.0, 800MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- ONFI IO v3.2, 533MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- Standard Cell (ECO) Library IP, RVT, UMC 55nm SP process