UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
Overview
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
55nm
Related IPs
- OSC Crystal Oscillator Low Power Series
- Low Power PLL for TSMC 40nm ULP
- Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
- On-Chip IO to Core Voltage Buck Regulator on UMC 55nm ULP
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU