UMC 55nm LP process with PG Dual port SRAM compiler
Overview
UMC 55nm LP process with PG Dual port SRAM compiler
Technical Specifications
Foundry, Node
UMC 55nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
55nm
Related IPs
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- HHGrace 0.11um LP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler