UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
Overview
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/uLP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing