UMC 55nm EFLASH Process Two Port Register File
Overview
UMC 55nm EFLASH Process Two Port Register File
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/LP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
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- Two Port Register File compiler - Memory optimized for high density and low power optimized - compiler range up to 40 k
- Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k