UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
Overview
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/LP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- 55nm eFlash Dual-Port SRAM memory compiler with row redundancy
- UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
- UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
- UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler
- POR - SMIC 55nm Eflash