UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x000D_
Overview
UMC 55nm eFlash peocess One Port Register File memory compiler
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/LP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 0.162um eFalsh/LL One Port Register File_x005F_x000D_ memory compiler
- TSMC CLN7FF Synchronous One Port Register File Compiler
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- Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
- Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
- Single Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 40 k