UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
Overview
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
Technical Specifications
Foundry, Node
UMC 28nm Logic/Mixed_Mode HPC
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
Related IPs
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- High Density Single Port Multi-banks SRAM Compiler
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits