UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
Overview
UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
Technical Specifications
Foundry, Node
UMC 28nm
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- 12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
- DDR4 multiPHY in UMC (28nm)
- MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)