UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
Overview
UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
Technical Specifications
Foundry, Node
UMC 0.45um Logic/Mixed_Mode Generic
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler.
- UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
- Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k